| SL $X,$Y,$Z | SL $X,$Y,Z |
| SLU $X,$Y,$Z | SLU $X,$Y,Z |
| SR $X,$Y,$Z | SR $X,$Y,Z |
| SRU $X,$Y,$Z | SRU $X,$Y,Z |
Specification:
| SL: s($X) | ← s($Y) × 2u($Z) |
| SLU: u($X) | ← (u($Y) × 2u($Z)) mod 264 |
| SR: s($X) | ← ⌊s($Y) / 2u($Z)⌋ |
| SRU: u($X) | ← ⌊u($Y) / 2u($Z)⌋ |
Timing:
1υ
Description:
SL shifts the bits in register $Y left. If bits unequal to the sign bit of $Y are shifted out during this process, an overflow is signaled. The result is filled with 0 bits from the right. SLU has the same effect but never causes overflow.
SR shifts the bits in register $Y to the right. It fills the target register from the left by replicating the sign bit and discards bits on the right; SRU fills the target register from the left with zeros.