<<<--- % Author M.Ruckert LOC #100 w IS $0 return value u IS$0 1. parameter v IS $1 2. parameter s IS$2 $w$ unpacked e IS $3 f IS$4 f0 IS $5 The low 64 bit of$f$carry IS$13 The shuttle between $f$ and $f_0$. su IS $6$u$unpacked eu IS$7 fu IS $8 sv IS$9 $v$ unpacked ev IS $10 fv IS$11 d IS $12$e_u - e_v$tmp IS$14 --->>> Fsub SETH tmp,#8000; XOR v,v,tmp Change sign of operand. Fadd SLU eu,u,1; SLU ev,v,1 Remove sign bit. CMPU tmp,eu,ev \ul{\sl A2.~Assume $e_u \ge e_v$.} BNN tmp,0F Branch if $(e_u, f_u) \ge (e_v, f_v)$ SET tmp,u; SET u,v; SET v,tmp else swap $u$ and $v$ SLU eu,u,1; SLU ev,v,1 and remove sign bit again. 0H SRU eu,eu,53; SRU ev,ev,53 \ul{\sl A1.~Unpack.} SETH tmp,#FFF0 Get sign and exponent mask. ANDN fu,u,tmp; ANDN fv,v,tmp Remove sign and exponent bits. INCH fu,#0010; INCH fv,#0010 Add hidden bit. SRU su,u,63; SRU sv,v,63 Get sign bit. SET e,eu; SET s,su \ul{\sl A3.~Set $e_w \is e_u$.} SUB d,eu,ev \ul{\sl A4.~Test $e_u-e_v$.} CMP tmp,d,53+2; BN tmp,5F $e_u-e_v \ge p+2$? SET f,fu; SET f0,0 $(f,f_0) \is f_u$ JMP 7F 5H NEG tmp,64,d \ul{\sl A5.~Scale right.} SLU f0,fv,tmp Shift $(f_v,f_0)$ to the right $e_u-e_v$ places SRU fv,fv,d CMP tmp,su,sv; BNZ tmp,0F Signs $s_u$ and $s_v$ differ. ADDU f,fu,fv \ul{\sl A6.~Add.} JMP 7F 0H NEGU f0,f0; ZSNZ carry,f0,1 \ul{\sl A6.~Subtract.} SUBU f,fu,fv; SUBU f,f,carry OR tmp,f,f0; BZ tmp,Error Result is zero. 7H IS @ \ul{\sl A7.~Normalize.} Normalize SRU tmp,f,53; BP tmp,4F \ul{\sl N1.~Test $f$.} If $f\ge 2$, scale right. OR tmp,f,f0; BZ tmp,Error underflow 2H SRU tmp,f,52; BP tmp,5F \ul{\sl N2.~Is $f$ normalized?} ZSN carry,f0,1; SLU f0,f0,1 \ul{\sl N3.~Scale left.} SLU f,f,1; ADDU f,f,carry SUB e,e,1 JMP 2B 4H AND carry,f,1 \ul{\sl N4.~Scale right.} SLU carry,carry,63 SRU f0,f0,1; ADDU f0,f0,carry SRU f,f,1 ADD e,e,1 5H SETH tmp,#8000 \ul{\sl N5.~Round.} CMPU tmp,f0,tmp Compare $f_0$ to ${1\over 2}$ CSOD carry,f,1 $f$ is odd. Round up if $f_0 \ge {1\over 2}$ CSEV carry,f,tmp $f$ is even. Round up if $f_0 > {1\over 2}$ ZSNN carry,tmp,carry Round down if $f_0 < {1\over 2}$ ADDU f,f,carry SET f0,0 SRU tmp,f,53; BP tmp,4B Rounding overflow SET tmp,#7FE; CMP tmp,e,tmp \ul{\sl N6.~Check $e$.} BP tmp,Error Overflow BNP e,Error Underflow SLU w,s,63 \ul{\sl N7.~Pack.} SLU tmp,e,52; OR w,w,tmp ANDNH f,#FFF0 remove hidden bit OR w,w,f <<<--- SET $0,w POP 1,0 Main NEG$2,100 FLOT $2,$2 FLOT $3,103 PUSHJ$1,Fadd % FLOT $2, % PUSHJ$0,Fsub SET $255,0 TRAP 0,Halt,0 Error SET$255,1 TRAP 0,Halt,0 --->>>