MMIX LOGO

MMIX Opcodes

Table of Content

Content

MMIX Opcodes

  #0 #1 #2 #3 #4 #5 #6 #7  
#0xTRAP FCMP υ FUN υ FEQL υ FADD FIX FSUBFIXU#0x
FLOT[I] 4υ FLOTU[I] 4υ SFLOT[I] 4υ SFLOTU[I] 4υ
#1xFMUL FCMPE FUNE υ FEQLEFDIV 40υFSQRT 40υ FREMFINT#1x
MUL[I] 10υ MULU[I] 10υ DIV[I] 60υ DIVU[I] 60υ
#2x ADD[I] υ ADDU[I] υ SUB[I] υ SUBU[I] υ #2x
2ADDU[I] υ 4ADDU[I] υ 8ADDU[I] υ 16ADDU[I] υ
#3x CMP[I] υ CMPU[I] υ NEG[I] υ NEGU[I] υ #3x
SL[I] υ SLU[I] υ SR[I] υ SRU[I] υ
#4x BN[B] υ + π BZ[B] υ + π BP[B] υ + π BOD[B] υ + π #4x
BNN[B] υ + π BNZ[B] υ + π BNP[B] υ + π BEV[B] υ + π
#5xPBN[B] 3υ - π PBZ[B] 3υ - π PBP[B] 3υ - π PBOD[B] 3υ - π #5x
PBNN[B] 3υ - π PBNZ[B] 3υ - π PBNP[B] 3υ - π PBEV[B] 3υ - π
#6x CSN[I] υ CSZ[I] υ CSP[I] υ CSOD[I] υ #6x
CSNN[I] υ CSNZ[I] υ CSNP[I] υ CSEV[I] υ
#7x ZSN[I] υ ZSZ[I] υ ZSP[I] υ ZSOD[I] υ #7x
ZSNN[I] υ ZSNZ[I] υ ZSNP[I] υ ZSEV[I] υ
#8x LDB[I] μ + υ LDBU[I] μ + υ LDW[I] μ + υ LDWU[I] μ + υ #8x
LDT[I] μ + υ LDTU[I] μ + υ LDO[I] μ + υ LDOU[I] μ + υ
#9x LDSF[I] μ + υ LDHT[I] μ + υ CSWAP[I] 2μ + 2υ LDUNC[I] μ + υ #9x
LDVTS[I] υ PRELD[I] υ PREGO[I] υ GO[I] 3υ
#Ax STB[I] μ + υ STBU[I] μ + υ STW[I] μ + υ STWU[I] μ + υ #Ax
STT[I] μ + υ STTU[I] μ + υ STO[I] μ + υ STOU[I] μ + υ
#Bx STSF[I] μ + υ STHT[I] μ + υ STCO[I] μ + υ STUNC[I] μ + υ #Bx
SYNCD[I] υ PREST[I] υ SYNCID[I] υ PUSHGO[I] 3υ
#Cx OR[I] υ ORN[I] υ NOR[I] υ XOR[I] υ #Cx
AND[I] υ ANDN[I] υ NAND[I] υ NXOR[I] υ
#Dx BDIF[I] υ WDIF[I] υ TDIF[I] υ ODIF[I] υ #Dx
MUX[I] υ SADD[I] υ MOR[I] υ MXOR[I] υ
#ExSETH υ SETMH υ SETML υ SETL υ INCH υ INCMH υ INCML υ INCL υ #Ex
ORH υ ORMH υ ORML υ ORL υ ANDNH υ ANDNMH υ ANDNML υANDNL υ
#Fx JMP[B] υ PUSHJ[B] υ GETA[B] υ PUT[I] υ #Fx
POPRESUME [UN]SAVE 20μ + υ SYNC υ SWYM υ GET υ TRIP
  #8 #9 #A #B #C #D #E #F  

Example:

  • LDBU with register Operand: #82.
  • LDBU with immediate Operand: #83.
  • LDTU with register Operand: #8A.
  • LDTU with immediate Operand: #8B.

Timing:

  • υ one MMIX cycle
  • μ one MMIX memory access
  • π = 2υ if branch is taken π = 0, if branch is not taken

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