MMIX Instruction Set

Floating Point Arithmetic

FADD $X,$Y,$Z
FSUB $X,$Y,$Z
FMUL $X,$Y,$Z
FDIV $X,$Y,$Z
FREM $X,$Y,$Z
FSQRT $X,$Z
FINT $X,$Z

Specification:

FDIV:	f($X)	← f($Y) ∕ f($Z)
FREM:	f($X)	← f($Y) rem f($Z)
		y rem z is defined as y-nz, where n is the integer number closest to y∕z, or the closest even number in case of multiple closest integers.
FINT:	f($X)	← f(int(f($Z)))
FSQRT:	f($X)	← f($Z)1∕2

Timing:

4υ for FADD, FSUB, FMUL, FREM and FINT
40υ for FDIV and FSQRT

Description:

FADD, FSUB, FMUL, and FDIV perform arithmetic on floating point numbers. FINT rounds a floating point number to the nearest integer number using the current rounding mode. Unlike FIX, the result is still in floating point format. The instructions FINT and FSQRT can use the optional Y-Operand to specify a rounding mode: ROUND_OFF, ROUND_UP, ROUND_DOWN, or ROUND_NEAR.

The seven IEEE floating point arithmetic operations (addition, subtraction, multiplication, division, remainder, square root, and nearest-integer) all share common features, called the standard floating point conventions in the discussion below: The operation is performed on floating point numbers found in two registers, $Y and $Z, except that square root and integerization involve only one operand. If neither input operand is a NaN, we first determine the exact result, then round it using the current rounding mode found in special register rA. Infinite results are exact and need no rounding. A floating overflow exception occurs if the rounded result is finite but needs an exponent greater than 2046. A floating underflow exception occurs if the rounded result needs an exponent less than 1 and either

(i) the unrounded result cannot be represented exactly as a subnormal number or
(ii) the "floating underflow TRIP" is enabled in rA.

NaNs are treated specially as follows: If either $Y or $Z is a signaling NaN, an invalid exception occurs and the NaN is quieted by adding 1/2 to its fraction part. Then if $Z is a quiet NaN, the result is set to $Z; otherwise if $Y is a quiet NaN, the result is set to $Y. (Registers $Y and $Z do not actually change.)

FADD:	"floating add". The floating point sum $Y + $Z is computed by the standard floating point conventions just described, and placed in register $X. An invalid exception occurs if the sum is (+∞) + (-∞) or (-∞) + (+∞); in that case the result is NaN(1/2) with the sign of $Z. If the sum is exactly zero and the current mode is not rounding-down, the result is +0.0 except that (-0.0) + (-0.0) = -0.0. If the sum is exactly zero and the current mode is rounding-down, the result is -0.0 except that (+0.0)+(+0.0) = +0.0. These rules for signed zeros turn out to be useful when doing interval arithmetic: If the lower bound of an interval is +0.0 or if the upper bound is -0.0, the interval does not contain zero, so the numbers in the interval have a known sign. Floating point underflow cannot occur unless the U-trip has been enabled, because any underflowing result of floating point addition can be represented exactly as a subnormal number.
FSUB:	"floating substract". This instruction is equivalent to FADD, but with the sign of $Z negated unless $Z is a NaN.
FMUL:	"floating multiply". The floating point product $Y x $Z is computed by the standard floating point conventions, and placed in register $X. An invalid exception occurs if the product is (±0.0) x (±∞) or (±∞) x (±0.0); in that case the result is ±NaN(1/2). No exception occurs for the product (±∞) x (±∞). If neither $Y nor $Z is a NaN, the sign of the result is the product of the signs of $Y and $Z.
FDIV:	"floating divide". The floating point quotient $Y/$Z is computed by the standard floating point conventions, and placed in $X. A floating divide by zero exception occurs if the quotient is (normal or subnormal)/(±0.0). An invalid exception occurs if the quotient is (±0.0)/(±0.0) or (±∞)/(±∞); in that case the result is ±NaN(1/2). No exception occurs for the quotient (±∞)/(±0.0). If neither $Y nor $Z is a NaN, the sign of the result is the product of the signs of $Y and $Z. If a floating point number in register $X is known to have an exponent between 2 and 2046, the instruction INCH $X,#fff0 will divide it by 2.0.
FREM:	"floating remainder". The floating point remainder $Y rem $Z is computed by the standard floating point conventions, and placed in register $X. (The IEEE standard defines the remainder to be $Y -n x $Z, where n is the nearest integer to $Y/$Z, and n is an even integer in case of ties. This is not the same as the remainder $Y mod $Z computed by DIV or DIVU.) A zero remainder has the sign of $Y. An invalid exception occurs if $Y is infinite and/or $Z is zero; in that case the result is NaN(1/2) with the sign of $Y.
FSQRT:	"floating square root". The floating point square root √$Z is computed by the standard floating point conventions, and placed in register $X. An invalid exception occurs if $Z is a negative number (either infinite, normal, or subnormal); in that case the result is -NaN(1/2). No exception occurs when taking the square root of -0.0 or +∞. In all cases the sign of the result is the sign of $Z. The Y field of FSQRT can be used to specify a special rounding mode.
FINT:	"floating integer". The floating point number in register $Z is rounded (if necessary) to a floating point integer, using the current rounding mode, and placed in register $X. Infinite values and quiet NaNs are not changed; signaling NaNs are treated as in the standard conventions. Floating point overflow and underflow exceptions cannot occur. The Y field of FINT can be used to specify a special rounding mode.